The present invention relates generally to integrated circuit devices (chips) and more specifically to techniques for distributing and synchronizing clock signals on a chip.
As semiconductor chips grow larger and faster, the need to control the timing becomes increasingly important. Many different functional portions of the chip are designed to be operating in a known time relationship to each other, and it is a fundamental assumption that a given clock signal at one portion of the chip will be substantially synchronized with the same clock signal at another portion of the chip. To the extent that the possibility of different delay times was recognized, a typical way of achieving a measure of synchronization was to attempt to equalize the various clock distribution lines. This is feasible, but becomes difficult when a large number of clock signals need to be synchronized at a number of locations on a large chip.
A further problem with high-speed processor chips is that they dissipate more power. While suitable heat sinks can avoid problems associated with the heat generated, the problem of power consumption remains. This can be a major issue with portable computers which run off a battery.